Integrated: 8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

[Fei Yang]

On Wed, 14 Sep 2022 03:09:16 GMT, Fei Yang <fyang at openjdk.org> wrote:

> This is similar to https://bugs.openjdk.org/browse/JDK-8293351
> Add a second temporary register for BarrierSetAssembler::load_at GC API on riscv64.
> Today G1 and Shenandoah uses a second temporary register. This will also be the case for generational ZGC.
> 
> Testing: Tier1-3 tested on Linux-riscv64 SiFive Unmatched board.

This pull request has now been integrated.

Changeset: 7376c552
Author:    Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/7376c55219ce2107afb9197e2452e7122d86ef52
Stats:     327 lines in 13 files changed: 9 ins; 108 del; 210 mod

8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

Reviewed-by: fjiang, shade

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PR: https://git.openjdk.org/jdk/pull/10261