RFR: 8294087: RISC-V: Refactor instruction alignment assertions

[Feilong Jiang]

On Wed, 21 Sep 2022 03:54:03 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> This is a trivial refactoring for some instruction alignment assertions. Due to the fact that the `assert (__ offset() % 4 == 0)` is getting used more, this small patch is extracted first to simplify code reviewing.
> This patch doesn't change the code behavior.
> Tested hotspot tier1 and tier2 together with other patches on QEMU.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 94:

> 92: }
> 93: 
> 94: void MacroAssembler::assert_alignment() {

It's a bit weird that `assert_alignment` only checks the alignment of instruction size. Can you extend this method with a parameter like `align_size` to check any alignment? (instruction size can be the default size of the check)

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PR: https://git.openjdk.org/jdk/pull/10370