RFR: 8294087: RISC-V: RVC: Fix a potential alignment issue and add more alignment assertions for the patchable calls/nops [v5]

[Fei Yang]

On Wed, 21 Sep 2022 14:51:52 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> With RVC turning on, we must carefully keep all runtime-patchable instructions aligned. Code is running at full speed, when patching unaligned instructions spanning cache lines, concurrency issues may occur. This patch fixes a potential alignment issue of the patchable nop after MachUEPNode, with adding some strong alignment assertions as well. (In fact, currently the `nop` in the Verified Entry Point is fortunately aligned to 4 under RVC even without this patch, so this patch doesn't change program behaviors.)
>> 
>> Tested hotspot tier1 and tier2 together with other patches on QEMU.
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix a plural form typo in one comment

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 101:

> 99:   assert(is_aligned(pc, alignment), "bad alignment");
> 100: }
> 101: 

Would you mind a few more tweaks?
I don't think we need two versions here. Maybe we can only keep the second one and remove the first one here?
Then the call sites will look more consistent passing an explict 'pc' argument.
Also we should move the function definition to macroAssembler_riscv.hpp.

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PR: https://git.openjdk.org/jdk/pull/10370