RFR: 8313322: RISC-V: implement MD5 intrinsic [v2]

[Robbin Ehn]

On Mon, 31 Jul 2023 16:05:13 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

>> What the title says. I started with the aarch64 version but changed it quite heavily.
>> 
>> I haven't done anything with the macro assembler before, so detailed / picky feedback is very welcome!
>
> Antonios Printezis has updated the pull request incrementally with one additional commit since the last revision:
> 
>   changes based on code review feedback

Thanks, looks good to me!

You also have some tests here:
test/hotspot/jtreg/compiler/intrinsics/sha/sanity/TestMD5xxx

I'll take it for a spin.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1975:

> 1973:   assert_different_registers(dst, tmp);
> 1974:   assert_different_registers(src, tmp);
> 1975:   assert(shift < 64, "shift amount must be < 64");

shift should probably be less than 32.

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 599:

> 597:     assert_cond(dest != nullptr);                                                                        \
> 598:     int64_t offset = dest - pc();                                                                        \
> 599:     guarantee(is_simm13(offset) && ((offset % 2) == 0),                                                  \

bool is_even(intx x) instead of mod ?

-------------

PR Review: https://git.openjdk.org/jdk/pull/15090#pullrequestreview-1556160780
PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1280106727
PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1280121528