RFR: 8313322: RISC-V: implement MD5 intrinsic [v2]

[Ludovic Henry]

On Mon, 31 Jul 2023 16:05:13 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

>> What the title says. I started with the aarch64 version but changed it quite heavily.
>> 
>> I haven't done anything with the macro assembler before, so detailed / picky feedback is very welcome!
>
> Antonios Printezis has updated the pull request incrementally with one additional commit since the last revision:
> 
>   changes based on code review feedback

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1972:

> 1970: 
> 1971: // rotate left with shift bits, 32-bit version
> 1972: void MacroAssembler::rol32_imm(Register dst, Register src, uint32_t shift, Register tmp) {

You could actually name it `rolw_imm` so that you can easily match it to [rolw](https://github.com/riscv/riscv-bitmanip/blob/6d33919c661a838f6ae89a05650b3ee6aa303440/bitmanip/insns/rolw.adoc#L3) when Zbb is available.

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PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1280173799