RFR: 8312569: RISC-V: Missing intrinsics for Math.ceil, floor, rint [v2]

[Feilong Jiang]

On Fri, 18 Aug 2023 13:06:05 GMT, Ilya Gavrilin <duke at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/riscv.ad line 7706:
>> 
>>> 7704:   match(Set dst (RoundDoubleMode src rmode));
>>> 7705:   ins_cost(2 * XFER_COST + BRANCH_COST);
>>> 7706:   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
>> 
>> Do we kill `cr` anywhere in the assembly code?
>
> According to documentation we have situations when convert instruction can set an error flag in the status register:
>> All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. [1] 
> 
> [1] https://five-embeddev.com/riscv-isa-manual/latest/f.html#single-precision-floating-point-conversion-and-move-instructions

There is no dedicated flag register on risc-v. We choose `t1` as the flag register to bridge the RegFlag semantics in share and opto. Kill `cr` here is not needed since nowhere uses `t1` as tmp register.
https://github.com/openjdk/jdk/blob/3e1b1bf94e7acf9717b837085e61fc05a7765de4/src/hotspot/cpu/riscv/riscv.ad#L404-L407

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PR Review Comment: https://git.openjdk.org/jdk/pull/14991#discussion_r1301571670