RFR: 8318217: RISC-V: C2 VectorizedHashCode [v10]

[Yuri Gaevsky]

On Fri, 8 Dec 2023 03:51:49 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Yuri Gaevsky has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Added two temp registers for loads; all loads in wide loop has been moved to the start of the loop.
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1504:
> 
>> 1502:   andi(cnt, cnt, stride-1); // don't forget about tail!
>> 1503: 
>> 1504: #define DO_ELEMENT_LOAD(reg, idx) \
> 
> Why not turn `DO_ELEMENT_LOAD` macro into a small function? Say `C2_MacroAssembler::arrays_hashcode_elload`. We can put it after `C2_MacroAssembler::arrays_hashcode_elsize`.

Good idea, will do, thanks.

> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1541:
> 
>> 1539: 
>> 1540:   bind(TAIL);
>> 1541:   beqz(cnt, DONE);
> 
> `cnt` is non-zero we reach here from L1498, so this `beqz` check seems redundant in that case. Maybe move this `beqz` check immediate after L1538?

We need this check because after wide "unrolling" loop the cnt could be 0,1,2 or 3, see "don't forget about tail" comment at the line 1502.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1420098364
PR Review Comment: https://git.openjdk.org/jdk/pull/16629#discussion_r1420097330