RFR: 8320397: RISC-V: Avoid passing t0 as temp register to MacroAssembler:: cmpxchg_obj_header/cmpxchgptr [v2]

[Robbin Ehn]

On Thu, 14 Dec 2023 10:24:42 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Yeah, I agree it is error-prone. But it is the same case for ther other platforms which have a real CR register, isn't it? They should have the same issue. I guess it doesn't deserve it if we keep `t1` the dedicated CR register, that is not touched else where by other masm assembers.
>
> I think we can pretty easy add a scoped object, similar to uncompressed region, where we can white-list registers.
> 
> So the ad file would add for example to fast_lock:
> 
> 
> {
>   AllowAdditionalRegister(t1); // As we kill cr fastlock may use t1/(cr) in addition to t0 and passed in regs.
>   ___ fastlock(...);
> }

Anyhow something to think about.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16880#discussion_r1426529344