RFR: 8319716: RISC-V: Add SHA-2 [v2]

[Robbin Ehn]

On Thu, 14 Dec 2023 13:31:43 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 1359:
>> 
>>> 1357:   }
>>> 1358: 
>>> 1359:   inline void vmsltu_vi(VectorRegister Vd, VectorRegister Vs2, int32_t imm, VectorMask vm = unmasked) {
>> 
>> Seems this function is not used in the code?
>> And, when `imm` == 0, seems it will output unexpected value?
>
> We can keep it as it's a good complement to existing methods and the cost is very low. Good point on `imm == 0`, we should probably have an assert for that case or have a `splat(false)` operation.

Fixed

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1427851962