RFR: 8319716: RISC-V: Add SHA-2 [v2]

[Ludovic Henry]

On Fri, 1 Dec 2023 19:09:46 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains four additional commits since the last revision:
>> 
>>  - Flag fixes
>>  - Merge branch 'master' into sha256
>>  - Share code
>>  - SHA-2
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 1359:
> 
>> 1357:   }
>> 1358: 
>> 1359:   inline void vmsltu_vi(VectorRegister Vd, VectorRegister Vs2, int32_t imm, VectorMask vm = unmasked) {
> 
> Seems this function is not used in the code?
> And, when `imm` == 0, seems it will output unexpected value?

We can keep it as it's a good complement to existing methods and the cost is very low. Good point on `imm == 0`, we should probably have an assert for that case or have a `splat(false)` operation.

> src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 1363:
> 
>> 1361:   }
>> 1362: 
>> 1363:   inline void vmsgeu_vi(VectorRegister Vd, VectorRegister Vs2, int32_t imm, VectorMask vm = unmasked) {
> 
> Same comments as `vmsltu_vi ` above.

It's used at https://github.com/openjdk/jdk/pull/16562/files#diff-97f199af6d1c8c17b2fa4f50eb1bbc0081858cc59a899f32792a2d31f933ccc4R3945.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1426722994
PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1426721667