RFR: 8322179: RISC-V: Implement SHA-1 intrinsic [v2]

[Hamlin Li]

On Mon, 18 Dec 2023 13:56:42 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Add some comments
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4592:
> 
>> 4590: 
>> 4591:     __ slli(tmp1, b, 32);
>> 4592:     __ andi(prev_ab, a, mask32, tmp2);
> 
> I think this will materialize `mask32` in `tmp2` twice, once per `andi`, given that the value won't work as an intermediate. I'd do `__ mv(tmp2, mask32)` and use `__ andr(prev_ab, a, tmp2)` and `__ andr(prev_cd, c, tmp2)`. I think it will save 2-3 instructions here. No idea how performance-critical this section is, though! I assume not much?

Good suggestion.
And, I use a dedicated register to hold the 0xffffffff now, as the value is needed in the busy loop for multiple times.

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4664:
> 
>> 4662: 
>> 4663:     RegSet saved_regs = RegSet::range(x18, x27);
>> 4664:     saved_regs += RegSet::of(t2);
> 
> Do you need to save t2?

deleted.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1431743579
PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1431746005