RFR: 8319716: RISC-V: Add SHA-2 [v8]

[Robbin Ehn]

On Thu, 21 Dec 2023 20:13:04 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   index store state back
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3790:
> 
>> 3788:     //  the cost of moving those vectors at the end of each quad-rounds.
>> 3789:     void sha2_quad_round(Assembler::SEW vset_sew, VectorRegister rot1, VectorRegister rot2, VectorRegister rot3, VectorRegister rot4,
>> 3790:                          Register scalarconst, VectorRegister vtemp, VectorRegister vtemp2, VectorRegister vtemp3, VectorRegister vtemp4,
> 
> maybe rename `vtemp3` -> `v_abef`, `vtemp4` -> `v_cdgh`

Good, thanks, fixed.

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3803:
> 
>> 3801:       }
>> 3802:       if (gen_words) {
>> 3803:         __ vsha2ms_vv(rot1, vtemp2, rot4);
> 
> when `gen_words == false` && `step_const  == true`, is it necessary to call `vmerge_vvm(vtemp2, rot3, rot2);` above?

Great find, thanks, fixed.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1435060694
PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1435060878