RFR: 8319716: RISC-V: Add SHA-2 [v8]

[Robbin Ehn]

On Thu, 21 Dec 2023 20:20:38 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   index store state back
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3792:
> 
>> 3790:                          Register scalarconst, VectorRegister vtemp, VectorRegister vtemp2, VectorRegister vtemp3, VectorRegister vtemp4,
>> 3791:                          bool gen_words = true, bool step_const = true) {
>> 3792:       __ vl1reXX_v(vset_sew, vtemp, scalarconst);
> 
> Seems we only incr `scalarconst ` conditionally, so load into `vtemp ` here could also be conditionally?

We need to load the constants, but this is the last round so we don't need to step constant forward.
Hence increment for next round.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1435057502