RFR: 8284196: RISC-V: Detect supported ISA extensions over cpuinfo [v2]
Ludovic Henry
luhenry at openjdk.org
Tue Feb 7 08:37:50 UTC 2023
On Tue, 7 Feb 2023 03:07:16 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:
>> Currently, `elf_hwcap` for RISC-V only sets single-letter extension bit (e.g. IMAFD).
>> As many standard multi-letter ISA extensions are ratified (e.g. Zba/Zbb/Zbc/Zbs),
>> we should find a stable way to detect these supported ISA extensions in JVM.
>> [1] has proposed a way to parse supported extensions through /proc/cpuinfo
>> or "riscv,isa" string of /sys/firmware/devicetree, we could detect supported extensions
>> in the same way.
>>
>> Here is an example of /proc/cpuinfo with multi-letter extensions from Ubuntu 20.04 in QEMU-SYSTEM:
>>
>>
>> ubuntu at ubuntu:~$ uname -a
>> Linux ubuntu 5.8.0-14-generic #16~20.04.3-Ubuntu SMP Mon Feb 1 16:33:19 UTC 2021 riscv64 riscv64 riscv64 GNU/Linux
>> ubuntu at ubuntu:~$ cat /proc/cpuinfo
>> processor : 0
>> hart : 2
>> isa : rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_sstc
>> mmu : sv48
>>
>>
>> 1: http://lists.infradead.org/pipermail/linux-riscv/2021-November/010252.html
>>
>>
>> Testing:
>> - [x] `jdk/bin/java -XX:+UnlockExperimentalVMOptions -XX:+UseZihintpause -XX:+UseRVV -XX:+UseZicbop -XX:+UseZba -XX:+UseZbb -XX:+UseZbs -XX:+PrintFlagsFinal -version` with release build
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>
> fix typo
Changes requested by luhenry (Committer).
src/hotspot/cpu/riscv/vm_version_riscv.cpp line 186:
> 184: }
> 185:
> 186: if (UseZba && !_cpu_features.ext_zba) {
We are missing where we are implicitly enabling `UseZ*` based on their corresponding values in `_cpu_feature.ext_z*`. I would assume it to be the main motivator for this change.
src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp line 103:
> 101: void VM_Version::get_isa() {
> 102: char isa_buf[500];
> 103: strcpy(isa_buf, _isa);
You should use `snprintf(isa_buf, sizeof(isa_buf), "%s", _isa)` to make sure it fits in `isa_buf` and it's `\0` terminated.
src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp line 113:
> 111: while (base_ext[i] != '\0') {
> 112: const char ch = base_ext[i++];
> 113: if (ch == 'i') {
Nit: You can use a `switch` case here, easier to read IMO.
-------------
PR: https://git.openjdk.org/jdk/pull/12343
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