RFR: 8284196: RISC-V: Detect supported ISA extensions over cpuinfo [v2]

[Feilong Jiang]

On Tue, 7 Feb 2023 08:20:27 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

> There are also other proposals in Linux, like the `riscv_hwprobe` syscall [1] which should also be supported in glibc. 
> [1] https://lkml.org/lkml/2023/2/6/1147

Thanks for the information, great to see some progress being made.

> Relying on `/proc/cpuinfo` which comes from the device tree is I think a good first step.

Yes, it would be better than hwcap which only represents single-letter cpu features, and that's why I create this PR.
When I first implemented this part of the code, I searched for the proper way to detect features but only found hwcap,
so I left a TODO in `get_os_cpu_info`. I also find this slide [1] discussed how to represent all RISC-V ISA features (I think hwcap2 looks promising). There is further progress about hwcap2 in [2], so when this feature is ready, we can switch to a better solution in the future.

[1] https://lpc.events/event/11/contributions/1103/attachments/832/1576/Puzzle%20for%20RISC-V%20ifunc.pdf
[2] https://lpc.events/event/16/contributions/1168/attachments/1055/2075/The%20Odyssey%20of%20HWCAP%20on%20RISC-V%20platforms%20with%20Palmer%27s%20Porosal%20in%20Backups.pdf

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PR: https://git.openjdk.org/jdk/pull/12343