RFR: 8301036: RISC-V: Factor out functions baseOffset & baseOffset32 from MacroAssembler

[Ludovic Henry]

On Wed, 25 Jan 2023 04:50:40 GMT, Fei Yang <fyang at openjdk.org> wrote:

> The functions baseOffset & baseOffset32 from MacroAssembler on RISC-V receive an Address in base_plus_offset mode. They check the range of the offset, add it and base and put the result in a destination register. This duplicates function MacroAssembler::la in functionality. We could refactor this part putting the logic of Address legitimization into MacroAssembler::la and use this function instead.
> 
> Testing:
>   - [x] Bootcycle (release & fastdebug)
>   - [x] Tier1-4 (release)
>   - [x] Benchmarks: SPECjbb2015 (release)

src/hotspot/cpu/riscv/interp_masm_riscv.cpp line 263:

> 261:                                                                int bcp_offset,
> 262:                                                                size_t index_size) {
> 263:   assert(cache != tmp, "should be different registers");

It could be worth replacing with `assert_different_registers`

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2394:

> 2392: 
> 2393:   assert(Rd != noreg, "expecting a register");
> 2394:   guarantee(Rd != base, "should be different registers");

Why not `assert`?

-------------

PR: https://git.openjdk.org/jdk/pull/12177