RFR: 8311862: RISC-V: small improvements to slli

[Feilong Jiang]

On Tue, 11 Jul 2023 09:02:39 GMT, Ilya Gavrilin <duke at openjdk.org> wrote:

> Please review this small change for slli and slli.uw
> slli change allows to replace slli Rd, Rs, 0 with addi Rd, Rs, 0 (and no operation emited if Rd == Rs)
> addi with 0 has higher chances to be just a register renaming and not utilise ALU at all
> We have observed small positive effect on hifive (and no change on thead).
> Also this patch changes slli.uw and allows it to be used without additional check for UseZba, also providing fallback when Zba is not available
> testing: tier1 and tier2 on hifive, also hotspot/jtreg/compiler/intrinsics/string tests on Qemu with UseZba
> 
> performance on hifive, before:
> |              Benchmark              | Mode | Cnt |   Score  |   |  Error  | Units |
> |:-----------------------------------:|:----:|:---:|:--------:|:-:|:-------:|:-----:|
> | StringIndexOf.advancedWithShortSub1 | avgt |  25 | 4035.143 | ± | 191.262 | ns/op |
> | StringIndexOf.advancedWithShortSub2 | avgt |  25 | 1145.807 | ± |  14.610 | ns/op |
> 
> with patch:
> |              Benchmark              | Mode | Cnt |   Score  |   |  Error  | Units |
> |:-----------------------------------:|:----:|:---:|:--------:|:-:|:-------:|:-----:|
> | StringIndexOf.advancedWithShortSub1 | avgt |  25 | 3613.943 | ± | 178.153 | ns/op |
> | StringIndexOf.advancedWithShortSub2 | avgt |  25 | 923.169 | ± |  47.123| ns/op |

Looks good, with one nit:

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4342:

> 4340:     _slli_uw(Rd, Rs, shamt);
> 4341:   } else {
> 4342:     slli(Rd, Rs, shamt+32);

Suggestion:

    slli(Rd, Rs, shamt + 32);

-------------

Marked as reviewed by fjiang (Author).

PR Review: https://git.openjdk.org/jdk/pull/14823#pullrequestreview-1525617190
PR Review Comment: https://git.openjdk.org/jdk/pull/14823#discussion_r1260670748