RFR: 8310268: RISC-V: misaligned memory access in String.Compare intrinsic [v7]

[Vladimir Kempik]

On Wed, 26 Jul 2023 03:41:47 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Vladimir Kempik has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   reduce registers usage and nits
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 917:
> 
>> 915:     }
>> 916:     addi(cnt2, cnt2, isUL ? 4 : 8);
>> 917:     bne(tmp1, tmp2, DIFFERENCE);
> 
> You might want to place this `bne` before the preceding `addi(cnt2, cnt2, isUL ? 4 : 8);`

Doubt so. Current code allows cnt2 to be calculated by the time the "bgez(cnt2, TAIL);" executed, if the cpu can execute two opcodes at once. So it benefits inorder dual-issue cpus (like hifive u74/unmatched)

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/14534#discussion_r1274501152