RFR: 8313322: RISC-V: implement MD5 intrinsic

[Ludovic Henry]

On Mon, 31 Jul 2023 13:50:10 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

> What the title says. I started with the aarch64 version but changed it quite heavily.
> 
> I haven't done anything with the macro assembler before, so detailed / picky feedback is very welcome!

Could you also indicate which test suite you've run to validate the change?

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3917:

> 3915: 
> 3916:   // Set of L registers that correspond to a contiguous memory area.
> 3917:   // Each 64-byte register typically corresponds to 2 32-byte integers.

`64-byte` -> `64bits`, same for `32-byte`.

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3940:

> 3938:     }
> 3939: 
> 3940:     // Generate code extracting i-th unsigned word (4 bytes) from cached 64 bytes.

`64 bytes` -> `64 bits`

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3954:

> 3952:   typedef RegCache<8> BufRegCache;
> 3953: 
> 3954:   void rotate_left_32(Register rd, Register rs, uint bits, Register rtmp1, Register rtmp2) {

That could be in `macroAssembler_riscv.hpp`

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PR Review: https://git.openjdk.org/jdk/pull/15090#pullrequestreview-1554988952
PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1279426146
PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1279427048
PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1279427681