RFR: 8313322: RISC-V: implement MD5 intrinsic

[Antonios Printezis]

On Mon, 31 Jul 2023 14:52:30 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> What the title says. I started with the aarch64 version but changed it quite heavily.
>> 
>> I haven't done anything with the macro assembler before, so detailed / picky feedback is very welcome!
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3917:
> 
>> 3915: 
>> 3916:   // Set of L registers that correspond to a contiguous memory area.
>> 3917:   // Each 64-byte register typically corresponds to 2 32-byte integers.
> 
> `64-byte` -> `64bits`, same for `32-byte`.

64-byte register! Will fix.

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3940:
> 
>> 3938:     }
>> 3939: 
>> 3940:     // Generate code extracting i-th unsigned word (4 bytes) from cached 64 bytes.
> 
> `64 bytes` -> `64 bits`

Actually, this was (almost) correct. The original class from aarch64 cached 8 64-bit values, so 64 bytes. But I generalized it, so I'll rephrase it.

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PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1279447499
PR Review Comment: https://git.openjdk.org/jdk/pull/15090#discussion_r1279451218