RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]

[Fei Yang]

On Tue, 30 May 2023 01:58:23 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

>> RISC-V branch and jump instructions use 64-bit registers instead of 32-bit 
>> versions in RV64I. We use test_bit to test if bit 31 is zero to determine if a
>> 32-bit register is less than zero currently.
>> 
>> However, there will be two instructions when we use test_bit to test bit
>> 31/63 without Zbs extension[1], we can just use sign_extend instead, which
>> only use one instruction.
>> 
>> At the same time, we also change some 32-bit symbolic extension operations to
>> sign_extend for better readability.
>> 
>> [1] https://github.com/openjdk/jdk/blob/e21f865d84c7c861843ff568019e1ad11d280a50/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L4596-L4603
>> 
>> ## Testing:
>> Unmatched:
>> - [x] Tier1 tests (release)
>> - [x] Tier2 tests (release)
>> - [x] Tier3 tests (release)
>
> Dingli Zhang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix some comments

Changes requested by fyang (Reviewer).

src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp line 985:

> 983:       __ sign_extend(dest->as_register(), src->as_register(), 8); break;
> 984:     case Bytecodes::_l2i:
> 985:       _masm->block_comment("FIXME: This could be a no-op");

We should remove this block comment as it's not applicable for riscv here.

-------------

PR Review: https://git.openjdk.org/jdk/pull/14197#pullrequestreview-1449970331
PR Review Comment: https://git.openjdk.org/jdk/pull/14197#discussion_r1209636370