RFR: 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit [v2]

[Dingli Zhang]

On Tue, 30 May 2023 01:57:41 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Dingli Zhang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix some comments
>
> src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp line 985:
> 
>> 983:       __ sign_extend(dest->as_register(), src->as_register(), 8); break;
>> 984:     case Bytecodes::_l2i:
>> 985:       _masm->block_comment("FIXME: This could be a no-op");
> 
> We should remove this block comment as it's not applicable for riscv here.

Thanks! Fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/14197#discussion_r1209639583