RFR: 8318158: RISC-V: implement roundD/roundF intrinsics [v2]

[Andrew Haley]

On Sat, 11 Nov 2023 10:43:35 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> It won't because of double rounding, and changing rounding modes is expensive. 
>> https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L5882
>
> But doing fadd 0.5 to the number, which can't have fractional part, in rdn mode becomes no-op.
> At least on single precision floats it works:
> fadd(-8388609.0, +0.5, rdn) results in -8388609.0
> and the mode for both fadd and fcvt will be the same, (perf tests showed no difference on thead tho)

Maybe. I didn't try it, but on a great big out-of-order machine changing floating-point modes can be fantastically expensive, forcing ops in progress to retire, changing mode, and then continuing. Effectively it's as bad as a mispredict. Given that a correct solution that doesn't involve changing modes is available, I don't see why you wouldn't use it.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16382#discussion_r1390371225