RFR: 8318953: RISC-V: Small refactoring for MacroAssembler::test_bit [v2]

[Gui Cao]

On Fri, 27 Oct 2023 07:19:00 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Use and_imm12 to replace andi in test_bit
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4678:
> 
>> 4676:   int64_t imm = (int64_t)(1UL << bit_pos);
>> 4677:   if (is_simm12(imm)) {
>> 4678:     andi(Rd, Rs, imm);
> 
> Since `imm` is guaranteed to be a signed 12-bit immediate in this block, we could call `and_imm12` more directly instead of `andi`.

Thanks for your review. fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16391#discussion_r1374174249