RFR: 8318953: RISC-V: Small refactoring for MacroAssembler::test_bit

[Fei Yang]

On Fri, 27 Oct 2023 06:52:54 GMT, Gui Cao <gcao at openjdk.org> wrote:

> Hi, The current test_bit assembly function needs to accept a temporary register because it needs one if it goes to the andi else branch. However, in this case we can actually avoid calling andi and accomplish the same thing by logically shifting to the right and testing the lowest bit. The advantage is that it makes the test_bit function much simpler. Also, to reduce the number of instructions in a given case (consider the mv function), mv actually calls the li function, which generates more than one instruction when the parameter imm exceeds the 32-bit range.
> https://github.com/openjdk/jdk/blob/9123961aaa47aa58ec436640590d2cceedb8cbb1/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L2009-L2017
> https://github.com/openjdk/jdk/blob/9123961aaa47aa58ec436640590d2cceedb8cbb1/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp#L730
> https://github.com/openjdk/jdk/blob/9123961aaa47aa58ec436640590d2cceedb8cbb1/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp#L804-L840
> 
> ### Testing:
> qemu 8.1.50:
> - [ ] Tier1 tests (fastdebug)
> - [ ] Tier2 tests (release)
> - [ ] Tier3 tests (release)

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4678:

> 4676:   int64_t imm = (int64_t)(1UL << bit_pos);
> 4677:   if (is_simm12(imm)) {
> 4678:     andi(Rd, Rs, imm);

Since `imm` is guaranteed to be a signed 12-bit immediate in this block, we could call `and_imm12` directly instead of `andi`.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4681:

> 4679:   } else {
> 4680:     srli(Rd, Rs, bit_pos);
> 4681:     andi(Rd, Rd, 1);

Similar here: call `and_imm12` directly instead of `andi`

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PR Review Comment: https://git.openjdk.org/jdk/pull/16391#discussion_r1374166348
PR Review Comment: https://git.openjdk.org/jdk/pull/16391#discussion_r1374167066