RFR: 8315841: RISC-V: Check for hardware TSO support

[Vladimir Kempik]

On Thu, 7 Sep 2023 09:00:50 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

> With the Ztso extension [1], some hardware will support TSO on RISC-V. That allows us to reduce the generation of memory fences, given the stronger memory model compared to RVWMO.
> 
> [1] https://github.com/riscv/riscv-isa-manual/blob/6dcbc6da9ada01f0f57da83cda6059bdec57619f/src/ztso-st-ext.adoc#L1

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 381:

> 379:   void fence(uint32_t predecessor, uint32_t successor) {
> 380:     if (UseZtso) {
> 381:       // do not emit fence if it's not at least a StoreLoad fence

Could you improve the comment with some examples, next code is hard to read  "if ( not  (a and b)) then .."

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PR Review Comment: https://git.openjdk.org/jdk/pull/15613#discussion_r1318460146