RFR: 8315841: RISC-V: Check for hardware TSO support

[Ludovic Henry]

On Thu, 7 Sep 2023 09:00:50 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

> With the Ztso extension [1], some hardware will support TSO on RISC-V. That allows us to reduce the generation of memory fences, given the stronger memory model compared to RVWMO.
> 
> [1] https://github.com/riscv/riscv-isa-manual/blob/6dcbc6da9ada01f0f57da83cda6059bdec57619f/src/ztso-st-ext.adoc#L1

`fence ir,iorw` would not match `(predecessor & w) && (successor & r)`, leading to not generating the fence. In the end, only the following fences would be generated: `rw,r`, `rw,rw` `w,r`, `w,rw`.

Some of the most common cases of fences that are going to be generated are `fence w,r` (used for `sun.misc.Unsafe::fullFence`) and `fence rw,rw` (generated for `MacroAssembler::AnyAny`).

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PR Comment: https://git.openjdk.org/jdk/pull/15613#issuecomment-1709970098