RFR: 8315841: RISC-V: Check for hardware TSO support [v4]

[Andrew Haley]

On Thu, 7 Sep 2023 12:00:30 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> With the Ztso extension [1], some hardware will support TSO on RISC-V. That allows us to reduce the generation of memory fences, given the stronger memory model compared to RVWMO.
>> 
>> [1] https://github.com/riscv/riscv-isa-manual/blob/6dcbc6da9ada01f0f57da83cda6059bdec57619f/src/ztso-st-ext.adoc#L1
>
> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fixup! 8315841: RISC-V: Check for hardware TSO support

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 392:

> 390:     Assembler::fence(predecessor, successor);
> 391:   }
> 392: 

Suggestion:

  void fence(uint32_t predecessor, uint32_t successor) {
    if (UseZtso) {
      if (pred_succ_to_membar_mask(predecessor, successor) & StoreLoad) {
        // TSO allows for stores to be reordered after loads. When the compiler
        // generates a fence to disallow that, we are required to generate the
        // fence for correctness.
        Assembler::fence(predecessor, successor);
      } else {
        // TSO guarantees other orderings already.
      }
    }
  }

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PR Review Comment: https://git.openjdk.org/jdk/pull/15613#discussion_r1318533009