RFR: 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit

[Hamlin Li]

On Wed, 18 Dec 2024 00:47:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Hi, please review this small improvement.
> 
> When `step` is 16, the `andi` instruction in the loop performs a bitwise AND with immediate mask value 0xFFFF. This will emit 3 instructions. It's effectively a zero extension operation and could be reduced to 1 or 2 instructions repectively depending on whether Zbb extension is available. And there is no difference when `step` is 8 with this change.
> 
> Testing: tier1 and gtest:all are clean on Premier-P550 SBC running Ubuntu-24.04.

Sorry, just realize this.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 5404:

> 5402:                               Register tmp1, Register tmp2) {
> 5403:   if (UseZbb) {
> 5404:     assert_different_registers(Rd, Rs, tmp1);

Is it necessary for Rd/Rs be different registers? similar question for the assert below.

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PR Review: https://git.openjdk.org/jdk/pull/22800#pullrequestreview-2511652525
PR Review Comment: https://git.openjdk.org/jdk/pull/22800#discussion_r1890136404