RFR: 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit [v2]

[Fei Yang]

On Wed, 18 Dec 2024 12:10:51 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Review comments
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 5404:
> 
>> 5402:                               Register tmp1, Register tmp2) {
>> 5403:   if (UseZbb) {
>> 5404:     assert_different_registers(Rd, Rs, tmp1);
> 
> Is it necessary for Rd/Rs be different registers? similar question for the assert below.

Good question. I don't think it's necessary to put `Rs` on the list. But we need to swap the two `mv`s for the second assertion in case `Rd` and `Rs` are the same. I also renamed `ctzc_bit` to `ctzc_bits` as appropriate and added code comments for the callsites. Please take another look. Thanks.

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PR Review Comment: https://git.openjdk.org/jdk/pull/22800#discussion_r1890236776