RFR: 8346475: RISC-V: Small improvement for MacroAssembler::ctzc_bit [v2]

[Hamlin Li]

On Wed, 18 Dec 2024 13:29:18 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hi, please review this small improvement.
>> 
>> When `step` is 16, the `andi` instruction in the loop performs a bitwise AND with immediate mask value 0xFFFF. This will emit 3 instructions. It's effectively a zero extension operation and could be reduced to 1 or 2 instructions repectively depending on whether Zbb extension is available. And there is no difference when `step` is 8 with this change.
>> 
>> Testing: tier1 and gtest:all are clean on Premier-P550 SBC running Ubuntu-24.04.
>
> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Review comments

Another comment.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 5408:

> 5406:     ctz(Rd, Rs);
> 5407:     andi(tmp1, Rd, step - 1);
> 5408:     sub(Rd, Rd, tmp1);

Seems these 2 lines can be replaced with single instruction:

andi Rd, Rd, -step

-------------

PR Review: https://git.openjdk.org/jdk/pull/22800#pullrequestreview-2511957263
PR Review Comment: https://git.openjdk.org/jdk/pull/22800#discussion_r1890305395