RFR: 8322179: RISC-V: Implement SHA-1 intrinsic [v9]

[Hamlin Li]

On Mon, 5 Feb 2024 12:51:24 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   not pass in temp register explicitly
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4951:
> 
>> 4949:       __ add(cur_w, cur_k, cur_w);
>> 4950:       __ add(t, t, cur_w);
>> 4951:       __ rolw_imm(cur_w, a, 5, t1);
> 
> Since `rolw_imm` uses `t0` as the default temp register, I think a more simpler `__ rolw_imm(cur_w, a, 5);` will do? This also makes `t1` available in places where `tmp` is used (and thus frees t2).

Not sure, as t0/t1 already used in sha1_f, so `tmp` (`dst` in sha1_f) seems must be another passed-in register.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1480023134