RFR: 8322179: RISC-V: Implement SHA-1 intrinsic [v9]

[Hamlin Li]

On Tue, 6 Feb 2024 15:22:42 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4951:
>> 
>>> 4949:       __ add(cur_w, cur_k, cur_w);
>>> 4950:       __ add(t, t, cur_w);
>>> 4951:       __ rolw_imm(cur_w, a, 5, t1);
>> 
>> Since `rolw_imm` uses `t0` as the default temp register, I think a more simpler `__ rolw_imm(cur_w, a, 5);` will do? This also makes `t1` available in places where `tmp` is used (and thus frees t2).
>
> Not sure, as t0/t1 already used in sha1_f, so `tmp` (`dst` in sha1_f) seems must be another passed-in register.

It's changed to `rolw_imm(cur_w, a, 5, t0);`, as IMHO implicit default temp register is error-prone.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1480038816