RFR: 8322179: RISC-V: Implement SHA-1 intrinsic [v9]

[Hamlin Li]

On Tue, 6 Feb 2024 14:42:43 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   not pass in temp register explicitly
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4832:
> 
>> 4830:   //    M't,                                      0 <=  t <= 15
>> 4831:   //    ROTL'1(W't-3 ^ W't-8 ^ W't-14 ^ W't-16),  16 <= t <= 79
>> 4832:   void sha1_prepare_w(int round, Register cur_w, Register ws[], Register buf, Register tmp) {
> 
> It seems that we could use `t1` in places where `tmp` is used. Maybe we could further remove this `tmp` formal param (and thus frees `t2`)? Together with the above comment, hopefully, we can free register `t2` and let `src` alias this instead of `x9` thus saving one register saving/restoring respectively on stub entry/exit.

Updated, thanks!
But still kept t2, as we need it in sha1_process_round/sha1_f.

> test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java line 72:
> 
>> 70:     public static final BooleanSupplier SHA1_INSTRUCTION_AVAILABLE
>> 71:             = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha1" }, null),
>> 72:               // on riscv64, SHA-1 intrinsic is implemented with basic instructions
> 
> How about rephasing this as: `// SHA-1 intrinsic is implemented with scalar instructions on riscv64`?

Yes, it's better.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1480040300
PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1480036728