RFR: 8319716: RISC-V: Add SHA-2 [v10]

[Fei Yang]

On Fri, 22 Dec 2023 14:10:13 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi, please consider.
>> 
>> Main author is @luhenry, I only fixed some minor things and tested it.
>> 
>> Such as:
>> test/hotspot/jtreg/compiler/intrinsics/sha/
>> test/jdk/java/security/MessageDigest/
>> test/jdk/jdk/security/
>> tier1
>> 
>> And still running some test.
>
> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fixed lmul

Hi, Thanks for the update. Having another look :-)

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3792:

> 3790:                          Register scalarconst, VectorRegister vtemp, VectorRegister vtemp2, VectorRegister v_abef, VectorRegister v_cdgh,
> 3791:                          bool gen_words = true, bool step_const = true) {
> 3792:       __ vl1reXX_v(vset_sew, vtemp, scalarconst);

Shouldn't we use `vleXX_v` to load the constant for each round instead of `vl1reXX_v`? `vl1reXX_v` which delegates work to `vl1re32_v`/vl1re64_v only loads a single vector register and is not aware of the LMUL setting. I see the openssl version is using `vle32_v`/`vle64_v` to load 4 e32/e64 elements of the constants for each round.

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3934:

> 3932:       //
> 3933:       // e32/e64: vector of 32b/64b/4B/8B elements
> 3934:       // m1: LMUL=1

This line of comment needs to be updated to reflect the latest changes.

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PR Review: https://git.openjdk.org/jdk/pull/16562#pullrequestreview-1795378708
PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1439171039
PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1435451464