RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v2]

[ArsenyBochkarev]

On Mon, 8 Jul 2024 14:50:00 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> ArsenyBochkarev has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Use t2 directly instead of temp2
>>  - Rename temp1 -> x0
>>  - Left a note on a side effect of generate_vle32_pack4
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2332:
> 
>> 2330:     const Register key         = c_rarg2;  // key array address
>> 2331:     const Register keylen      = c_rarg3;
>> 2332:     const Register x0          = c_rarg4;
> 
> I think you can use the global `x0` (aka the zero register) instead for `vsetivli`. It very confusing to have register alias names like `x0` like here.

Done

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1677133451