RFR: 8320646: RISC-V: C2 VectorCastHF2F [v3]

[Fei Yang]

On Mon, 4 Mar 2024 11:52:40 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1995:
>> 
>>> 1993:   auto stub = C2CodeStub::make<VectorRegister, VectorRegister, uint>
>>> 1994:               (dst, src, length, 24, float16_to_float_v_slow_path);
>>> 1995: 
>> 
>> I think we should add one assertion here asserting that `dst` and `src` are differenct vector registers.
>
> we could, but it's not necessary, as in `riscv_v.ad` it already has:
> 
> instruct vconvHF2F(vReg dst, vReg src, vRegMask_V0 v0) %{
>   ...
>   effect(TEMP_DEF dst, TEMP v0);

We always do that in practice. An explicit assertion will help people better understand the code when they are solely looking at these assember functions. Otherwise they will have to check the caller side about the constraint on register usage. Also it could happen in the future that the same code might be reused or called from other newly-added code. It will help avoid errors on passing registers when people see such an assertion on entry.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17698#discussion_r1512096823