RFR: 8320646: RISC-V: C2 VectorCastHF2F [v3]

[Hamlin Li]

On Tue, 5 Mar 2024 12:05:16 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Here is what I read from the RVV 1.0 spec [1]: 
>> 
>> 
>> The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (srl) and
>> sign-extending (sra) forms. The shift amount can come from a vector register group, or a scalar x register, or
>> a zero-extended 5-bit immediate. 
>> 
>> A zero-extended 5-bit immediate will have a maximum of 31. 
>> 
>> [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-narrowing-integer-right-shift-instructions
>
> You're right!
> But, we have this code for `vnsra_wi` on riscv: `guarantee(is_simm5(imm), "imm is invalid"); `, we need to correct it, I'll do it.

Fixed, thanks!

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PR Review Comment: https://git.openjdk.org/jdk/pull/17698#discussion_r1513009326