RFR: 8340241: RISC-V: Returns mispredicted [v5]

[Robbin Ehn]

On Wed, 9 Oct 2024 08:31:10 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Updated asserts
>
> src/hotspot/cpu/riscv/assembler_riscv.hpp line 2895:
> 
>> 2893:   // All calls and jumps must go via MASM.
>> 2894:   void jalr(Register Rd, Register Rs, const int32_t offset) {
>> 2895:     assert(Rd != x5 && Rs != x5, "Register x5 not used for calls/jumps.");
> 
> Suggestion:
> 
>     assert(Rd != x5 && Rs != x5, "Register x5 should not be used for calls/jumps.");

Updated

> src/hotspot/cpu/riscv/assembler_riscv.hpp line 2910:
> 
>> 2908: 
>> 2909:   void jal(Register Rd, const int32_t offset) {
>> 2910:     assert(Rd != x5, "Register x5 not used for calls/jumps.");
> 
> Suggestion:
> 
>     assert(Rd != x5, "Register x5 should not be used for calls/jumps.");

Updated

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 944:
> 
>> 942: void MacroAssembler::load_link_jump(const address source, Register temp) {
>> 943:   assert(temp != noreg && temp != x0, "expecting a register");
>> 944:   assert(temp != x5, "Register x5 not used for calls.");
> 
> Suggestion:
> 
>   assert(temp != x5 && temp != x1, "Register x5/x1 should not be used for jumps.");

Updated

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1012:
> 
>> 1010: void MacroAssembler::jr(Register Rd, int32_t offset) {
>> 1011:   assert(Rd != noreg, "expecting a register");
>> 1012:   assert(Rd != x5, "Register x5 not used for jumps.");
> 
> Same as above:
> Suggestion:
> 
>   assert(temp != x5 && temp != x1, "Register x5/x1 should not be used for jumps.");

Updated

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1020:
> 
>> 1018:   assert_cond(dest != nullptr);
>> 1019:   assert(temp != noreg, "expecting a register");
>> 1020:   assert(temp != x5, "Register x5 not used for jumps.");
> 
> Same as above:
> Suggestion:
> 
>   assert(temp != x5 && temp != x1, "Register x5/x1 should not be used for jumps.");

Updated

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1029:
> 
>> 1027: void MacroAssembler::jalr(Register Rs, int32_t offset) {
>> 1028:   assert(Rs != noreg, "expecting a register");
>> 1029:   assert(Rs != x1, "expecting a register");
> 
> Same as above:
> Suggestion:
> 
>   assert(temp != x5 && temp != x1, "Register x5/x1 should not be used for jumps.");

Updated

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1035:
> 
>> 1033: 
>> 1034: void MacroAssembler::rt_call(address dest, Register tmp) {
>> 1035:   assert(tmp != x5, "Register x5 not used for jumps.");
> 
> Same as above:
> Suggestion:
> 
>   assert(temp != x5 && temp != x1, "Register x5/x1 should not be used for jumps.");

Updated

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799308200
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799308324
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799308581
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799308686
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799308782
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799309066
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799308879