RFR: 8340241: RISC-V: Returns mispredicted [v6]

[Robbin Ehn]

On Wed, 9 Oct 2024 08:35:30 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Updated assert
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 973:
> 
>> 971:     Assembler::jal(x0, distance);
>> 972:   } else {
>> 973:     assert(temp != x5 && temp != x1, "Register x5/x1 not used for jumps.");
> 
> Suggestion:
> 
>     assert(temp != noreg && temp != x0, "expecting a register");
>     assert(temp != x5 && temp != x1, "Register x5/x1 should not be used for jumps.");
> 
> To keep the order consistent with https://github.com/openjdk/jdk/pull/21406/files#diff-7a5c3ed05b6f3f06ed1c59f5fc2a14ec566a6a5bd1d09606115767daa99115bdR943

Updated

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PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799313055