RFR: 8340241: RISC-V: Returns mispredicted [v10]

[Robbin Ehn]

On Tue, 15 Oct 2024 06:20:40 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Fixed no explicit use of default t1
>>  - Revert clinit_barrier t1
>
> src/hotspot/cpu/riscv/vtableStubs_riscv.cpp line 184:
> 
>> 182:   const Register temp_reg           = x28;
>> 183:   const Register temp_reg2          = x29;
>> 184:   const Register icdata_reg         = t0;
> 
> It seems to me quite risky to let `t0` hold CompiledICData. Here for this case, the `__ increment(Address(x18));` at L166 would clobber `t0` implicitly. I am wondering if we have another choice.
> 
> (Or maybe we can move `t0` which holds CompiledICData to `t1` on entry and use `t1` afterwards like before?)

Yes, I think I like that, thanks.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1800574247