RFR: 8340241: RISC-V: Returns mispredicted [v10]

[Robbin Ehn]

On Tue, 15 Oct 2024 07:06:14 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/vtableStubs_riscv.cpp line 184:
>> 
>>> 182:   const Register temp_reg           = x28;
>>> 183:   const Register temp_reg2          = x29;
>>> 184:   const Register icdata_reg         = t0;
>> 
>> It seems to me quite risky to let `t0` hold CompiledICData. Here for this case, the `__ increment(Address(x18))` at L166 would clobber `t0` implicitly. I am wondering if we have another choice.
>> 
>> (Or maybe we can move `t0` which holds CompiledICData to `t1` on entry and use `t1` afterwards like before?)
>
> Yes, I think I like that, thanks.

Fixed, take another look.

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PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1800809706