RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v7]

[Arseny Bochkarev]

On Thu, 26 Sep 2024 05:39:11 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

>> Arseny Bochkarev has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Multiversion decrypt intrinsic
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2370:
> 
>> 2368:     assert(reg_number <= 14, "reg_number should be less than or equal to working_vregs size");
>> 2369: 
>> 2370:     for (int i = 0; i < reg_number; i++) {
> 
> Hello, I have a question about the order of register handling in loops. Why is it in ascending order instead of descending? Here’s an example: https://github.com/riscv/riscv-crypto/blob/main/doc/vector/code-samples/zvkned.s.
>  And I look forward to your reply. Thanks.

Hi! It was in ascending order because I used different keys for encryption and decryption, while it is possible to use same set for both cases. Though both decryption implementations are functionally correct, the [current](https://github.com/openjdk/jdk/pull/19960/commits/c8ca05777a77c351d9c3d536ea11d7fd9af23e2c) one is more optimal

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PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1805517549