RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v7]

[Arseny Bochkarev]

On Wed, 25 Sep 2024 14:29:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Arseny Bochkarev has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Multiversion decrypt intrinsic
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2373:
> 
>> 2371:       __ vxor_vv(res, res, working_vregs[i]);
>> 2372:       __ vaesdm_vv(res, vzero);
>> 2373:     }
> 
> Seems that a lot more `vxor.vv` are emitted here compared with the openssl version [1]. I wonder if this could be further optimized. Or is there anything I missed? Thanks.
> 
> [1] https://github.com/openssl/openssl/blob/master/crypto/aes/asm/aes-riscv64-zvkned.pl#L279-L295

You're absolutely right, thanks! Turned out I missed the fact that we can just use the encryption keys in reversed order for decryption

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1805517579