RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v9]

[Fei Yang]

On Mon, 21 Oct 2024 14:41:57 GMT, Arseny Bochkarev <duke at openjdk.org> wrote:

>> Hello everyone! Please review this port of vector AES single block encryption/decryption intrinsics. On my QEMU with `Zvkned` extension enabled the `test/hotspot/jtreg/compiler/codegen/aes/TestAESMain.java` test is OK. I know that currently hardware implementing this extension is not available on the market but I suppose this PR can be a good starting point on supporting AES intrinsics for RISC-V in OpenJDK.
>
> Arseny Bochkarev has updated the pull request incrementally with four additional commits since the last revision:
> 
>  - Use RISCV64 instead of RISCV
>  - Fixed comment line
>  - Rename reg_number -> rounds in aes_loadkeys
>  - Fix typo

src/hotspot/share/opto/library_call.cpp line 7229:

> 7227:   // Intel's extension is based on this optimization and AESCrypt generates round keys by preprocessing MixColumns.
> 7228:   // However, ppc64 vncipher processes MixColumns and requires the same round keys with encryption.
> 7229:   // The ppc64 and RISCV64 stubs of encryption and decryption use the same round keys (sessionK[0]).

Nit: A small `riscv64` will do here.

// The ppc64 and riscv64 stubs of encryption and decryption use the same round keys (sessionK[0]).

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1810407702