RFR: 8339771: RISC-V: Reduce icache flushes [v2]

[Robbin Ehn]

On Thu, 19 Sep 2024 06:35:46 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/relocInfo_riscv.cpp line 61:
>> 
>>> 59:   if (!UseCtxFencei) {
>>> 60:     ICache::invalidate_range(addr(), bytes);
>>> 61:   }
>> 
>> One more question: Do we need a full fence (`OrderAccess::fence()`) here with `UseCtxFencei` after the patching? Like you do in `ZBarrierSetAssembler::patch_barrier_relocation()`:
>> 
>>   if (!UseCtxFencei) {
>>     // A full fence is generated before icache_flush by default in invalidate_word
>>     ICache::invalidate_range(addr, bytes);
>>   } else {
>>     OrderAccess::fence();
>>   }
>
> I actually didn't look at that.
> As the old case did a full fence when calling ICache::invalidate_range(addr, bytes); and with that comment,
> I assumed there was a reason for pointing it out, so I just kept the old behavior.
> I'll see If I can figure out if/why/what.

Sorry, now I realize what you are asking.

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PR Review Comment: https://git.openjdk.org/jdk/pull/20913#discussion_r1766241194