RFR: 8339771: RISC-V: Reduce icache flushes [v2]

[Fei Yang]

On Thu, 19 Sep 2024 06:38:24 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> I actually didn't look at that.
>> As the old case did a full fence when calling ICache::invalidate_range(addr, bytes); and with that comment,
>> I assumed there was a reason for pointing it out, so I just kept the old behavior.
>> I'll see If I can figure out if/why/what.
>
> Sorry, now I realize what you are asking.

The purpose is to make a store to instruction memory visible to all RISC-V harts.
Check this code in file icache_riscv.cpp:

static int icache_flush(address addr, int lines, int magic) {
  // To make a store to instruction memory visible to all RISC-V harts,
  // the writing hart has to execute a data FENCE before requesting that
  // all remote RISC-V harts execute a FENCE.I.

  // We need to make sure stores happens before the I/D cache synchronization.
  __asm__ volatile("fence rw, rw" : : : "memory");                           <==============

  RiscvFlushIcache::flush((uintptr_t)addr, ((uintptr_t)lines) << ICache::log2_line_size);

  return magic;
}

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PR Review Comment: https://git.openjdk.org/jdk/pull/20913#discussion_r1766245777