RFR: 8340732: RISC-V: Refactor crc32 scalar version

[Fei Yang]

On Wed, 25 Sep 2024 07:34:03 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 6097:
>> 
>>> 6095:     __ kernel_crc32(crc, buf, len,
>>> 6096:                     c_rarg3, c_rarg4, c_rarg5, c_rarg6, // tmp's for tables
>>> 6097:                     c_rarg7, t2, x28, x29, x30, x31);   // misc tmps
>> 
>> Nit: Can we use alias t3-t6 for x28-x31 instead? The purpose is to be consistent with `t2` in naming.
>
> How do you think we add t3-t6 alias into assemler_riscv.hpp?
> I saw several times people had the similar question, and in the code there are several places like this `Register size      = x29;   // t4`, i.e. try to use t3-t6, but needs to add a comment for that.

Ah, I just realized we only have t0 - t2 defined in file assemler_riscv.hpp. I think its reasonable and helpful to add more ones like t3 - t6. These are temporary registers names / ABI Mnemonics specified by the RISC-V psABI spec.

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PR Review Comment: https://git.openjdk.org/jdk/pull/21150#discussion_r1774709305