RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v7]

[Yanhong Zhu]

On Sun, 8 Sep 2024 13:24:49 GMT, Arseny Bochkarev <duke at openjdk.org> wrote:

>> Hello everyone! Please review this port of vector AES single block encryption/decryption intrinsics. On my QEMU with `Zvkned` extension enabled the `test/hotspot/jtreg/compiler/codegen/aes/TestAESMain.java` test is OK. I know that currently hardware implementing this extension is not available on the market but I suppose this PR can be a good starting point on supporting AES intrinsics for RISC-V in OpenJDK.
>
> Arseny Bochkarev has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Multiversion decrypt intrinsic

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2370:

> 2368:     assert(reg_number <= 14, "reg_number should be less than or equal to working_vregs size");
> 2369: 
> 2370:     for (int i = 0; i < reg_number; i++) {

Hello, I have a question about the order of register handling in loops. Why is it in ascending order instead of descending? Here’s an example: https://github.com/riscv/riscv-crypto/blob/main/doc/vector/code-samples/zvkned.s.
 And I look forward to your reply. Thanks.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1776411935