RFR: 8351949: RISC-V: Cleanup and enable store-load peephole for membars [v8]

[Robbin Ehn]

On Wed, 2 Apr 2025 13:16:05 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains 11 additional commits since the last revision:
>> 
>>  - Merge branch 'master' into tso-merge
>>  - Merge branch 'master' into tso-merge
>>  - format comment
>>  - Merge branch 'master' into tso-merge
>>  - Review comments
>>  - Merge branch 'master' into tso-merge
>>  - Review comments
>>  - Fixed ws
>>  - Revert NC
>>  - Fixed comment
>>  - ... and 1 more: https://git.openjdk.org/jdk/compare/18d961e2...c2688a6a
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3558:
> 
>> 3556: 
>> 3557: void MacroAssembler::membar(uint32_t order_constraint) {
>> 3558:   if (UseZtso && ((order_constraint & StoreLoad) != StoreLoad)) {
> 
> An assert in Assembler::fence() could help to catch potential misuse in the future:
> `assert(!UseZtso || ((order_constraint & StoreLoad) == StoreLoad)`

Sorry, I now understand, you mean after doing all these checks if we can elide.

Yes, that seems good.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24035#discussion_r2026281974